The present invention relates to a method for fabricating a thin film transistor, and more particularly to a method for fabricating a thin film transistor to be used as a switching element of a liquid crystal display device, enabling an easy fabrication and an improvement in device characteristic by use of a self-alignment.
Generally, thin film transistor-liquid crystal display (TFT-LCD) devices include a bottom plate formed with TFTs and pixel electrodes and a top plate formed with color filters and common electrodes. A liquid crystal is filled in a space defined between the upper plate and the lower plate. Polarizing plates for linearly polarizing visible rays are attached to opposed surfaces of the plates comprised of, for example, glass substrates, respectively.
FIG. 1a is a circuit diagram of an equivalent circuit of a general TFT-LCD array having the above-mentioned arrangement. FIG. 1b is a circuit diagram of an equivalent circuit of a unit pixel of the array shown in FIG. 1a.
As shown in FIG. 1a, the TFT-LCD device includes a plurality of gate signal lines G.sub.1 to G.sub.n each arranged between neighboring pixel regions in one direction, a plurality of data signal lines D.sub.1 to D.sub.n each arranged between neighboring pixel regions in a direction perpendicular to the direction of the gate signal lines, and a plurality of thin film transistors Q.sub.11 to Q.sub.nn each disposed at each corresponding pixel region and adapted to apply data voltage from each corresponding one of the data lines D.sub.1 to D.sub.n to each corresponding pixel electrode and liquid crystal in accordance with a signal from each corresponding one of the gate signal lines G.sub.1 to G.sub.n.
In each unit pixel of this TFT-LCD device, a capacitor C.sub.STO and an additional capacitor C.sub.LC are provided which are formed by virtue of the TFT serving as the switching element of the unit pixel and the liquid crystal present between the upper and lower plate electrodes.
In operation of the TFT-LCD device having the above-mentioned arrangement, a gate signal voltage is selectively applied to the TFT which is the switching element of each unit pixel. When the TFT receives the gate signal voltage, it is turned on so that data voltage carrying image information can be applied to the corresponding pixel electrode and the liquid crystal via the TFT for 2 hours.
As data voltage is applied to the TFT of each unit pixel, the arrangement of liquid crystal molecules is changed, resulting in a change in optical properties. As a result, an image is displayed.
In order to obtain high quality images in this TFT-LCD device, the display area for displaying an image, namely, the aperture ratio or the opening ratio should be large. Furthermore, the leakage current from the TFTs should be minimized.
For improving the aperture ratio, the area occupied by the TFT of each unit pixel should be reduced. This is because the region where the TFT of each unit pixel is formed can not display any image.
The data voltage which is applied to the pixel electrode of each unit pixel and the liquid crystal via the corresponding TFT has to be maintained for a predetermined time by the capacitors C.sub.STO and C.sub.LC provided by both the pixel electrode and the liquid crystal even when no gate signal voltage is applied.
In an ideal case, the total charge amount in the capacitors provided by the pixel electrode and the liquid crystal is maintained until a next signal is applied to the TFT which is at its turn-off state. In practical cases, however, a leakage of current occurs at the TFT. When such a leakage current is not sufficiently reduced, a distortion of liquid crystal voltage may occur, resulting in an occurrence of a flicker phenomenon.
Consequently, construction of TFTs is very important to achieve an improvement in aperture ratio and a decrease in leakage current both required for obtaining high quality images in TFT-LCD devices.
In other words, as the number of pixels is increased for obtaining a higher definition and a higher resolution in TFT-LCD devices, the dimension of each TFT should be reduced. Furthermore, the leakage current should be negligibly small.
Recently, research has been actively conducted to minimize the leakage current in small TFTs.
A conventional method for fabricating a TFT will be described in conjunction with FIGS. 2a to 2e.
This conventional method is used for fabricating an etch stopper type TFT.
In accordance with this method, an opaque metal layer made of Al, Ta or Cr is formed on an insulating transparent substrate 1 to provide a gate electrode 2, as shown in FIG. 2a. Over the entire exposed surface of the resulting structure, a gate insulating film 3, an amorphous silicon layer 4 and etch stopper layer 5 are sequentially deposited by a plasma enhanced chemical vapor deposition (PECVD) process. Thereafter, a photoresist film 9 is coated over the etch stopper layer 5.
Subsequently, the photoresist film 9 is subjected to a hard baking at a temperature of 110.degree. C. Using the gate electrode 2 as a mask, the resulting structure is subjected at the lower surface of the substrate 1 to a back light exposure by use of the self-alignment technique, as shown in FIG. 2b.
In this back light exposure, the positive photoresist film 9 is etched by a developer at its portion receiving light beams while partially remaining at its portion not receiving light beams because of the opaque gate electrode 2, namely, disposed just above the gate electrode 2. The remaining photoresist portion. Serves as a photoresist pattern.
At this time, the backward incident light beams are refracted inward of the gate electrode 2 at edges of the gate electrode 2 due to their scattering and diffraction phenomenons. As a result, the photoresist pattern has a dimension smaller than that of the pattern of the gate electrode 2.
Using the patterned photoresist film 9 as a mask, the etch stopper layer 5 is selectively removed at its exposed portion, as shown in FIG. 2c. At this time, the overlap length .DELTA.L between the gate electrode 2 and the etch stopper layer 5 is proportional to the energy of the incident light. For example, the overlap length .DELTA.L is less than 1 .mu.m at the incident light energy of 0.5 J/cm.sup.2.
Thereafter, an, amorphous silicon layer 6 doped with high concentration n-type impurity ions and a metal layer 7 are sequentially deposited over the entire exposed surface of the resulting structure, as shown in FIG. 2d.
The high concentration n-type amorphous silicon layer 6 and the metal layer 7 are selectively removed at their portions disposed over the etch stopper layer 5 so as to form source and drain electrodes 7a and 7b, as shown in FIG. 2e. Thus a TFT is obtained.
The operation of the TFT fabricated in accordance with the conventional method will now be described.
When a voltage not lower than the threshold voltage is applied to the gate electrode 2, a channel is formed at the interface between the amorphous silicon layer 4 and the gate insulating film 3, thereby causing the source and the drain to be electrically communicated with each other.
However, this conventional method has the following problems.
In the TFT which is used as the switching element in LCD devices, as shown in FIG. 3, a channel is generally formed at the interface between the gate insulating film and the amorphous silicon (a-Si) layer. As a result, where no overlap is present between the gate electrode and the source/drain electrodes, an offset region is formed between the amorphous silicon layer and the source electrode, thereby causing the TFT not to operate. On the contrary, where the overlap length is excessively large, the TFT is enlarged in dimension, thereby resulting in a decrease in aperture ratio. In addition, a parasitic capacitance may be present between the gate electrode and the source/drain electrode. When the TFT is turned off, such a parasitic capacitance affects the liquid crystal voltage due to its capacitive coupling. As a result, the liquid crystal voltage is varied by .DELTA.V, thereby resulting in a degradation in picture quality.
It is, accordingly, preferred that the overlap length between the gate electrode and the source/drain electrode is one to two .mu.m.
In the fabrication of TFTs in accordance with the conventional method, a back light exposure is carried out by utilizing the self-alignment technique under a condition that the single gate insulating film 3 has been formed and the gate electrode 2 is used as a mask. In this back light exposure, light beams are refracted inward of the gate electrode 2 at edges of the gate electrode 2 due to their scattering and diffraction phenomenons, as mentioned above. As a result, the overlap length of not less than one .mu.m can not be obtained, even though the pattern of the photoresist film 9 is smaller than the pattern of the gate electrode 2. To obtain an increased overlap length, the light exposure should be performed using high energy for a long time.
However, such a light exposure shortens the life of the exposure equipment and lengthens the time of the exposure process step. As a result, the yield is decreased.
Since only the etch stopper layer is etched by the self-alignment technique in accordance with the conventional method, the amorphous silicon layer serving as an active layer of the TFT has a width larger than that of the gate electrode. As a result, back light enters the amorphous silicon layer in the operation of the TFT-LCD device, thereby causing electrons to be excited in the amorphous silicon layer. This causes an increase in leakage current.
In particular, where the conventional method is used in the fabrication of LCDs for over head projectors requiring the quantity of light being forty times or above as large as those of LCDs for office automation, the leakage current is more increased while the ON/OFF ratio of TFT is decreased. As a result, a flicker phenomenon occurs, resulting in a degradation in LCD performance.